`timescale 1ns/1ns
module tb_fpadd;
reg [31:0] a,b;
reg [4:0] control;
wire [31:0] result;
wire [4:0] flags;


fpadd my_fpadd (
	a,
	b,
	result,
	control,
	flags);

initial
begin
control=5'b00000;
#100
a=32'h3e560000;b=32'h3e560000;
#100
a=32'h3e560000;b=32'hbf6d8000;
#100
a=32'hc3766b00;b=32'h43766b00;
#100 $stop;
end

endmodule